proteus的一个小定时计时， 时钟用的是6M，有源文件自己看-proteus a small regular time, the clock is 8h or 16h, active document that looks at 下载
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基于 CPU 的精确计时器，时钟频率越高，计时越准 -on CPU precision timer, clock frequency, the higher the more time - 下载
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基于CPLD的棋类比赛计时时钟,第一个CNT60实现秒钟计时功能，第二个CNT60实现分钟的计时功能，CTT3完成两小时的计时功能。秒钟计时模块的进位端和开关K1相与提供分钟的计时模块使能，当秒种计时模块计时到59时向分种计时模块进位，同时自己清零。同理分种计时模块到59时向CTT3小时计时模块进位，到1小时59分59秒时，全部清零。同时，开关K1可以在两小时内暂停秒钟计时模块，分钟计时模块和小时计时模块。各模块的VHDL语言描述如下：-CPLD-based time clock chess competitions, a CNT60 achieve seconds timing, CNT60 second minute of time to achieve functional, CTT3 completion of the two-hour time function. Module seconds into time - and-switch K1 phase minutes for a time module can be enabled When seconds time to time module to the 59 minute time rounding module, reset themselves. Similarly minute time module to the 59-hour time CTT3 module rounding to 1 hour 59 minutes 59 seconds, reset all. Meanwhile, switches K1 can be suspended within two hours time module seconds, minutes and hours of time metering module module. The module VHDL is described as follows : 下载
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基于_CPU_的精确计时器，时钟频率越高-_CPU_ based on the precision timer, the clock frequency is higher 下载
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FPGA时钟分析，包括门控时钟与时钟偏仪分析，逻辑设计时钟分析，毛刺分析．-FPGA clock analysis, including clock gating and clock partial analysis, logic design clock analysis, Burr analysis. 下载
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LCD液晶显示驱动模块液晶显示计时时钟单片机源程序-LCD display driver module LCD MCU time clock source 下载
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电子时钟显示系统设计电子时钟显示系统设计电子时钟显示系统设计-electronic clock display system design electronic clock display system design electronic clock display system design 下载
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用在51单片机上的时间程序，分时秒计时和显示的时钟，可以用键来调整，用iic发送到显示，刚学者用单片机做菜单和机器控制可以参考下。-51 microcontroller used in the time procedures, and time-of-use metering seconds of the clock shows that can be used to adjust the bond, use iic sent to show that scholars do MCU control menu and machines can refer to the next. 下载
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我自已设计的时钟程序-clock procedures 下载
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12887时钟计数器,提供标准的时钟,定时,显示时间- 下载
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