基于CPLD的FSK信号发生器的设计.PDF-based CPLD FSK signal generator design. PDF 下载
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FSK信号发生器，基于VHDL语言，好用的！- 下载
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FSK信号发生器,用于AD98XX等DDS芯片,能够更改频率- 下载
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FSK信号发生器,用于软件测试.采样率、波特率，幅度，f1，f2可调，不含wave头，样点类型I16，保存为文件-FSK signal generator for software testing. Sampling rate, baud rate, magnitude, f1, f2 adjustable, excluding the first wave, point-like type infarction, preservation of documents 下载
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dds信号发生器ask，am，fskdds信号发生器ask，am，fskdds信号发生器ask，am，fskdds信号发生器ask，am，fsk-dds signal generator ask, am, fskdds signal generator ask, am, fskdds signal generator ask, am, fskdds signal generator ask, am, FSK 下载
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用Verilog语言实现信号发生器，包括AM，FM,PM，ASK,PSK,FSK调制。-using Verilog language signal generator, including AM, FM, PM, ASK, PSK, FSK modulation. 下载
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2006altera大赛－基于软核Nios的宽谱正弦信号发生器设计：摘要：本设计运用了基于 Nios II 嵌入式处理器的 SOPC 技术。系统以 ALTERA公司的 Cyclone 系列 FPGA 为数字平台，将微处理器、总线、数字频率合成器、存储器和 I/O 接口等硬件设备集中在一片 FPGA 上，利用直接数字频率合成技术、数字调制技术实现所要求波形的产生，用 FPGA 中的 ROM 储存 DDS 所需的波形表，充分利用片上资源，提高了系统的精确度、稳定性和抗干扰性能。使用新的数字信号处理（DSP）技术，通过在 Nios 中软件编程解决 不同的调制方式的实现和选择。系统频率实现 1Hz～20MHz 可调，步进达到了1Hz；完成了调幅、调频、二进制 PSK、二进制 ASK、二进制 FSK 调制和扫频输出的功能。 -2006altera race-based soft-core Nios wide spectrum of sinusoidal signal generator design : Abstract : The use of design-based Nios II embedded processor SOPC technology. Altera Corporation system to the Cyclone FPGA series of digital platform, microprocessor, bus, Digital Frequency Synthesizer, memory and I / O interface hardware concentrated in an FPGA, the use of direct digital frequency synthesis technology and digital modulation waveforms required to achieve the rise, Using FPGA ROM storage of the DDS waveform table, and make full use of on-chip resources, improve the systems accuracy, stability and robustness. Use of new digital signal processing (DSP) technology, Nios through software programming to solve different ways of achieving modulation and choice. Realize the system freq 下载
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