MAXPLUS2 自己编写的VHDL 4位除法器-MAXPLUS2 prepare themselves VHDL four Divider 下载
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用vhdl实现的除法器。。。。。。。。。。。。- 下载
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用VHDL实现的除法器,非常好使,仿真通过了- 下载
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通过用硬件描述语言（VHDL）描述除法器，并进行模拟验证，加深对二进制数运算方法的理解。 设计平台：MaxPlusII 压缩文件内有详细设计报告 -by using Hardware Description Language (VHDL) Description division, and conduct simulation shows that the binary number deepen understanding of the operation. Design Platform : MaxPlusII compressed files with detailed design report 下载
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四位除法器的VHDL源程序-four division of VHDL source 下载
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这个是用vhdl语言编写的除法器,仅仅供大家参考.-the VHDL language is used to prepare for the division, just for reference. 下载
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VHDL 8位无符号除法器 试验报告 计算前在A和B端口输入被除数和除数，然后在Load线上送高电平，把数据存到除法计算电路内部，然后经过若干个时钟周期，计算出商和余数，并在C和D端输出。 其实现方法是，将除法器分为两个状态：等待状态与运算状态。 开始时除法器处于等待状态，在该状态，在每一时钟上升沿，采样Load信号线，若是低电平，则仍处于等待状态，如果采样到高电平，除法器读取A，B数据线上的输入数据，保存到内部寄存器a_r，b_r，置c_r为0，d_r为a_r，判断除数是否为零，若不为零则进入运算状态。 -VHDL eight unsigned divider calculation of the test report before the A and B ports to import and dividend divider, and then sent to I Load line, the data are uploaded to the internal division calculation circuit, and then after a number of clock cycles, and worked out more than a few, and in the C-and D output. Their method is to be divided into two division for the state : waiting for the state and Operational state. At the beginning divider waiting for the state, in the state in each clock rising edge, sampling Load signal line, if low-level, it is still waiting for the state, if the sampling to allow high output, Divider read A, B online data input data, preservation of the internal registers renovation r, b_r, home c_r 0, d_r a_r to determine whether the divisor zero, if not zero, it 下载
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一个用VHDL语言编写的除法器程序，对从事硬件开发的同志有帮助的。- 下载
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vhdl的几个编程，4位除法器的设计和原理说明，还有8位CPU设计-VHDL programming, the four division and the design principle that there are eight CPU Design 下载
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这是有关VHDL的相关源代码，有简易CPU、加法器、除法器、计数器等-This is the relevance of the VHDL source code, a simple CPU, Adder, Divider, counters, etc. 下载
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