串并转换VHDL程序源码压缩文件。解压后可获得源文件-Series and conversion procedures VHDL source compressed files. Unpacked available source 下载
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昨天在论坛上看到有人帖出了他写的并串转换VHDL代码，但是他自己说有问题，但是不知道怎么改。我大概看了一下，发现思路还是比较乱的。于是就写下了我自己的并串转换代码。-yesterday at the forum see someone points out his writing and string conversion VHDL code, But he said there are problems, but does not know how reform. I probably watched and found ideas is quite a mess. So I wrote on their own code and string conversion. 下载
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SDI接口的源程序,包括扰码编码,并串转换,用VHDL硬件描述语言编写-SDI interface of the source, including interference coding and string conversion, using VHDL hardware description language 下载
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VHDL，verilog串并转换源程序 Xilinx公司参考资料-VHDL, verilog Series and conversion company Xilinx reference source 下载
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用VHDL编写的并串转换和串并转换实例，希望对您有所帮助，其中输入数据是时钟的16倍-prepared using VHDL and string conversion and string conversion and examples, and I hope to help you, the input data which is 16 times the clock 下载
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VHDL代码，仿真通过，变异可以，下载变成文件，但需要修改，串并转换-VHDL code, through simulation, the variation can be downloaded into a document, but need to change, and change series 下载
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有此两文件是在MAXplusII环境下开发并运行通过的vhdl文件，实现了并串口转换功能。 [ref-sdr-sdram-vhdl.zip] - DDR控制器的vhdl源代码.采用FPGA实现DDR接口控制器,适用于Altera的-this document is in two MAXplusII environment through the development and operation of the vhdl documents, and the realization of serial conversion function. [Ref-sdr - sdram - vhdl.zip] - DDR controller vhdl source code. using FPGA DDR Interface Controller applies to the Altera 下载
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此两文件是在MAXplusII环境下开发并运行通过的VHDL文件，实现了并串口转换功能。-this document is in two MAXplusII environment through the development and operation of the VHDL documents, and the realization of serial conversion function. 下载
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通过多通道串-并转换器将多个同步串行数据流转换为并行数据-through multi-channel serial-to-parallel converter multiple synchronous serial data stream into parallel data 下载
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一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code 下载
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