PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), 数字锁相技术在通信领域应用非常广泛，本例用VHDL描述了一个锁相环作为参考，源码已经调试过。编译器synplicty.Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), the digital technology in the field of communications is widely used, the cases described in VHDL as a PLL reference source has been tuned. Compiler synplicty.Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the data locked up and the descending; Top-level document is PLL.GDF 下载
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PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF 下载
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easy pll,很好的PLL(锁相环设计工具)!- 下载
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锁相环设计文档和一个可执行文件............-PLL design documents and an executable file ............ 下载
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锁相与频率合成技术，庄卉等编著。讲述模拟和数字锁相环及频率合成器的理论、组成、测试和设计。-PLL frequency synthesizer with the technology, such as Zhuang Hui edited. On analog and digital PLL frequency synthesizer and the theory, composition, testing and design. 下载
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基于MC145159的PLL频率合成器设计与实现 介绍了锁相环路频率合成器的基本原理,分析了集成锁相环芯片M C 145159的工作特性,给出了集成锁相环芯片M C 145159的一个应用实例,为高频频率合成器的设计提供了一个较好的思路.测试结果证明了设计的合理性与实用性,系统频率稳定度优于10-7.-MC145159 PLL frequency synthesizer design and realization of PLL frequency synthesizer the basic principles of integrated PLL chip M C 145159 work characteristics, Integration is the PLL chip M C 145159 example of an application, for High Frequency Synthesizer Design provided a good idea. The test results proved the rationality of design and practicality. the system frequency stability is better than 10 -7. 下载
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基于PPGA的数字锁相环设计，在QUTEURS2下仿真通过-based on the 300MHz digital PLL design, simulation under through QUTEURS2 下载
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用于载波恢复的锁相环参数设计 很有用的哦,希望下载看看,对你有帮助的.... -for carrier recovery PLL parameters useful in the design Oh, look at the download, you have to help .... 下载
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为了测量 DVD的Jitter ,需要知道刻录时钟。针对 DVD 特殊的数据格式 NRZI,提出一个专用的时钟恢复系 统 ,用于从读出的 RF信号中恢复写时钟。这个系统采用基于锁相环的双环结构。介绍系统结构、各个模块的构成原理、数 学模型 ,并结合 Simulink 给出仿真结果。理论和实验证明 ,该系统既可作为测量 DVD Jitter 的硬件电路设计的参考 ,也可作 为软件设计的工具。-DVD to the Jitter measurement, the burning need to know the clock. DVD special against the NRZI data format, a dedicated clock to restore the system, From time for the RF signal was restored clock. The system based on the dual-loop PLL structure. On the structure, the various modules of the composition theory, mathematical model, and is integrated Simulink simulation results. Theory and experiment proved that the system can measure DVD Jitter as the hardware circuit design reference can also be used as the design of software tools. 下载
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