8位加法器VHDL 8位加法器VHDL 8位加法器VHDL 8位加法器VHDL 8位加法器VHDL-eight Adder VHDL eight Adder VHDL eight Adder VHDL eight Adder VHDL 8 Adder VHDL 下载
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VHD设计实例8位加法器的设计分频电路数字秒表的设计- 下载
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8位加法器的原代码,主要内容下载看了就知道-Adder eight of the original code, read the main content downloaded know 下载
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介绍8位加法器、分频电路、数字秒表的PPT，带源码，解释详细，一步一步学习，是学习VHDL的好东东-introduced eight Adder, the frequency divider circuit, digital stopwatch, the PPT, with the source code, explained in detail, step by step, learning, VHDL is a good learning Eastern 下载
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8位的加法器设计，分4个工程完成的，用的是Quartus II软件。-eight of the adder design, four hours to complete the project, using the Quartus II software. 下载
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verilog shi 实现的加法器（8位）适用于初学asic -Verilog realized Adder (8) applies to beginners blends 下载
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8位相位相加乘法器，具有高速，占用资源较少的优点-eight multiplier phase together with high-speed, taking up less resources advantages 下载
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单片机与扫描式键盘,LED实现的简易计算器,8位加减法,4位乘法-SCM and scanning keyboard, LED simple calculators, and subtract eight, four multiplication 下载
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一个用VHDL语言编写的8位全加器，并且扩展了减法功能，带有状态位的判断。-a VHDL prepared by the eight-adder, and extends the subtraction function, with state-of judgment. 下载
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大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital display, 74ls138, 8,4-bit counter, d, rs triggers, Adder, traffic lights, the original code based on the Yangtze University programmable devices experimental box, To run on other platforms need to be redefined pin 下载
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