采用verilog编写的串口通信程序，采用了状态机设计！程序简单，消耗资源少-Serial communication written by verilog hdl. It is designed with FSM. The program is simple,and consume resource is few. 下载
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拿verilog和vhdl编写的串口通信代码(可综合)-with vhdl and verilog prepared by the serial communication code (synthesis) 下载
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在微型计算机系统中, CPU与外部的基本通信方式有两种,一种是并行通信即数据的各位同 时传送,其优点是传输速度较快,但数据有多少位就需要多少条传送线 而串行通信中数据一位一位顺序传 送,能节省传送线. 用Verilog HDL语言实现了串并、并串通信接口之间的转换- 下载
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单片机或DSP硬件系统开发中，串行器件和串行通信经常要用到串口UART，本UART原代码有三个版本，分别用VHDL/VERILOG和LATICCE编写完成，并有详细的注释-MCU or DSP hardware system development, serial devices and serial communications to the regular use of serial UART, the UART original code has three editions, respectively VHDL / VERILOG and LATICCE completed, and a detailed Notes 下载
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